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rev 1.0, may 18, 2006 page 1 of 15 2 400 west cesar chavez, austin, tx 78701 1+(512) 416 - 8500 1+(512) 416 - 9669 www.silabs.com sl23ep08 key features ? 10 to 220 mhz operating frequency range ? low output clock skew: 45ps - typ ? low output clock jitter: ? 25 ps - typ cycle -to - cycle jitter ? 15 ps - typ period jitter ? low part -to - part output skew: 90 ps - typ ? wide 2.5 v to 3.3 v power supply ra nge ? low power dissipation: ? 20 ma - max at 66 mhz and vdd=3.3 v ? 18 ma - max at 66 mhz and vdd=2.5v ? one input drives 8 outputs ? multiple configurations and drive options ? select mode to bypass pll or tri - state outputs ? spreadthru ? pll that allows use of sscg ? available in 16 - pin soic and tssop packages ? available in commercial and industrial grades applications ? printers, mfps and digital copiers ? pcs and work stations ? routers, switchers and servers ? datacom and telecom ? high - speeddigit al embeded systems description the sl23ep08 is a low skew, low jitter and low power zero delay buffer (zdb) designed to produce up to nine (9) clock outputs from one (1) reference input clock, for high speed clock distribution applications. the product has an on - chip pll and a feedback pin (fbk) which can be used to obtain feedback from any one of the output clocks. the sl23ep08 has two (2) clock driver banks each with four (4) clock outputs. these outputs are controlled by two (2) select input pins s1 and s2. when only four (4) outputs are needed, four (4) bank - b output clock buffers can be tri - stated to reduce power dissipation and jitter. the select inputs can also be used to tri - state both banks a and b or drive them directly from the input bypassing the pll and making the product behave like a non - zero delay buffer (nzdb). the product also offers various 1x, 2x and 4x frequency options at the output clocks. refer to the ?product configuration table? for the details. the high - drive version operates up to 220mhz and 200mhz at 3.3v and 2.5v power supplies respectively. benefits ? up to eight (8) distribution of input clock ? standard and high - dirive levels to control impedance level, frequency range and emi ? low power dissipation, jitter and skew ? low cost bloc k diagram low power and low jitter pll mux input selection decoding logic vdd gnd 2 2 s2 s1 clkin fbk clka1 clka2 clka3 clka4 clkb1 clkb2 clkb3 clkb4 /2 /2 /2 (divider for -3 and -4 only) (divider for -5h only) (divider for -2 and -3 only) low jitter and skew 10 to 220 mhz zero delay buffer (zdb)
rev 1.0, may 18, 2006 page 2 of 15 sl23ep08 pin configuration clka1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 fbk clka4 clka3 vdd gnd clkb4 clkb3 s1 clkin clka2 vdd gnd clkb1 clkb2 s2 pin description 16 - pin soic and tssop pin number pin name pin type pin description 1 clkin input reference frequency clock input. 5v tolerant input. weak pull - down (2 50k). 2 clka1 output buffered clock output, bank a. weak pull - down (250k). 3 clka2 output buffered clock output, bank a. weak pull - down (250k). 4 vdd power 3.3v or 2.5v power supply. 5 gnd power power ground. 6 clkb1 output buffered clock out put, bank b. weak pull - down (250k). 7 clkb2 output buffered clock output, bank b. weak pull - down (250k). 8 s2 input select input, select pin s2. weak pull - up (250k). 9 s1 input select input, select pin s1. weak pull - up (250k). 10 clkb3 output b uffered clock output, bank b. weak pull - down (250k). 11 clkb4 output buffered clock output, bank b. weak pull - down (250k). 12 gnd power power ground. 13 vdd power 3.3v or 2.5v power supply. 14 clka3 output buffered clock output, bank a. weak p ull - down (250k). 15 clka4 output buffered clock output, bank a. weak pull - down (250k). 16 fbk output pll feedback input.
rev 1.0, may 18, 2006 page 3 of 15 sl23ep08 general description - the sl23ep08 is a low skew, low jitter zero delay buffer with very low operating current. the product inc ludes an on - chip high performance pll that locks into the input reference clock and produces nine (9) output clock drivers tracking the input reference clock for systems requiring clock distribution. in addition to clkout that is used for internal pll feed back, there are two (2) banks with four (4) outputs in each bank, bringing the number of total available output clocks to nine (9). input and output frequency range - the input and output freq uency range is the same. but, the frequency range depends on vd d and drive levels as given in the below table 1. vdd(v) drive min(mhz) max(mhz) 3.3 high 10 220 3.3 std 10 167 2.5 high 10 200 2.5 std 10 133 table 1. input/output frequency range if the input clock frequency is less than 2 mhz or floating, this i s detected by an input frequency det ection circuitry and all eight (8 ) clock outputs are forced to hi - z. the pll is shutdown to save power. in this shutdown state , the product draws less than 25 a supply current. spreadthru ? feature - if a spread spectrum clock (ssc) were to be used as an input clock, the sl23ep08 is designed to pass the modulated spread spectrum clock (ssc) signal from its reference input to the output clocks. the same spread characteristics at the input are passed through the pll and drivers without any degradation in spread percent (%), spread profile and modulation frequency select input control - the sl23ep08 provides two (2) input select cont rol pins called s1 and s2. this feature enables users to selects various states of output clock banks - a and bank - b, output source and pll shutdown features as shown in the table 2. the s1 (pin -9) and s2 (pin - 8) inputs include 2 50 k weak pull - down resistors to gnd. pll bypass mode if the s1 and s2 pins are logic low(0) and high(1) respectively, the on - chip pll is shutdown and bypassed, and all the nine output clocks bank a, bank b and clkout clocks are driven by directly fro m the reference input clock. in this operation mode sl23ep08 works like a non - zdb product. high and low - drive product options - the sl23ep08 is offered with high - drive ? - 1h? and standard - drive ? - 1? options. these drive options enable the users to contro l load levels, frequency range and emi control. refer to the ac electrical tables for the details. skew and zero delay - all outputs should drive the similar load to achieve output -to - output skew and input -to - output specifications given in the ac electri cal tables. however, zero delay between input and outputs can be adjusted by changing the loading of clkout relative to the banks a and b clocks since clkout is the feedback to the pll. power supply range (vdd) - the sl23ep08 is designed to operate in a w i de power supply range from 2.3v (min) to 3.3 v (max). an internal on - chip voltage regulator is used to supply pll constant power supply of 1.8v, leading to a consistent and stable pll electrical performance in terms of skew, jitter and power dissipation. c ontact sli for 1.8v power supply version zdb called sl23epl08. s2 s1 clock a1 - a4 clock b1 - b4 clkout output source pll shutdown and bypass 0 0 tri - state tri - state driven pll yes 0 1 driven tri - state driven pll no 1 0 driven [1] driven driven (4) [1] ref erence yes 1 1 driven driven driven pll no table 2. select input decoding
rev 1.0, may 18, 2006 page 4 of 15 sl23ep08 device feedback from bank - a frequency bank - b frequency sl23ep08 - 1 bank - a or bank - b reference reference sl23ep08 - 1h bank - a or bank - b reference reference sl23ep08 - 2 bank - a refere nce reference/2 sl23ep08 - 2 bank - b 2x reference reference sl23ep08 - 3 bank - a 2x reference reference [2] sl23ep08 - 3 bank - b 4x reference 2x reference sl23ep08 - 4 bank - a or bank - b 2x reference 2x reference sl23ep08 - 5h bank - a or bank - b reference /2 reference /2 table 3. available sl23ep08 configurations notes: 1. outputs are inverted on sl23ep08 - 2 and sl23ep08- 3 in pll bypass mode when s2=1 and s1=0. 2. output phase is either 0 or 180 with respect to clkin input. if phase integrity is require d, use the sl23ep08 -2. 0 5 10 15 20 25 30 -30 -25 -20 -5 -10 -15 1500 1000 500 -500 -1500 -1000 0 output load difference: fbk load ? clka or clkb load (pf) figure 1. clkin input to clka and clkb delay
rev 1.0, may 18, 2006 page 5 of 15 sl23ep08 absolute maximum ratings operating conditions: unless otherwise stated vdd=2.5v to 3.3v and for both c and i grades description condition min. max. unit supply voltage, vdd ? 0.5 4.6 v all inputs and outputs ? 0.5 vdd+0.5 v ambient ope rating temperature in operation, c - grade 0 70 c ambient operating temperature in operation, i - grade ? 40 85 c storage temperature no power is applied ? 65 150 c junction temperature in operation, power is applied ? 125 c soldering temperature ? 260 c esd rating (human body model) mil - std - 883, method 3015 2000 ? v symbol description condition min. max. unit vdd3.3 3.3v supply voltage 3.3v+/ - 10% 3.0 3.6 v vdd2.5 2.5v supply voltage 2.5v+/ - 10% 2.3 2.7 v ta operating temperature(ambient) commercial 0 70 c industrial ? 40 85 c cload load capacitance <100 mhz, 3.3v with standard or high drive ? 30 pf <100 mhz, 2.5v with high dri ve ? 30 pf <133.3 mhz, 3.3v with standard or high drive ? 22 pf <133.3 mhz, 2.5v with high drive ? 22 pf <133.3 mhz, 2.5v with standard drive ? 15 pf >133.3 mhz, 3.3v with standard or high drive ? 15 pf >133.3 mhz, 2.5v with high drive ? 15 pf cin input capacitance s1, s2 and clkin pins ? 5 pf clbw closed - loop bandwidth 3.3v, (typical) 1.2 mhz 2.5v, (typical) 0.8 mhz zout output impedance 3.3v, (typical), high drive 29 ? 3.3v, (typical), standard drive 41 ? 2.5v, (typical), high drive 37 ? 2.5v, (typical), standard drive 41 ?
rev 1.0, may 18, 2006 page 6 of 15 sl23ep08 dc electrical specifications (vdd=3.3v): unless otherwise stated for both c and i grades dc electrical specifications (vdd=2.5v): unless otherwise stated for both c and i grades symbol description condition min. max. unit vdd supply voltage 2.970 3.630 v vil input low voltage ? 0.8 v vih input high voltage 2.0 v dd +0.3 v iil input leakage current 0 < vin < 0.8v ? 10 a iih input high current vin = vdd ? 100 a vol output low voltage iol = 8 ma (standard drive) ? 0.4 v iol = 12 ma (high drive) ? 0.4 v voh output high voltage ioh = ? 8 ma (standard drive) 2.4 ? v ioh = ? 12 ma (high drive) 2.4 ? v iddpd power down supply curren t clkin<2mhz clkin = 0 mhz (c - grade) ? 12 a clkin = 0 mhz (i - grade) ? 25 a idd power supply current all outputs cl=0, 66 - mhz clkin ? 20 ma symbol description condition min. max. unit. vdd supply voltage 2.3 2.7 v vil input low voltage ? 0.7 v vih input high voltage 1.7 v dd + 0.3 v iil input leakage current 0 rev 1.0, may 18, 2006 page 7 of 15 sl23ep08 ac electrical specifications: vdd=3.3v +/ - 10% and 0c to +70c operation ( commercial grade ) symbol description condition min typ max unit fout -1 output frequency cl=30pf, all devices 10 - 160 mhz fout -2 output frequency cl=20pf, - 1h and - 5h versions 10 - 22 0 mhz fout -2 output frequency cl=15pf, -1, -2, - 3 and - 4 versions 10 - 20 0 mhz dc-1 duty cycle . - 1, - 2, -3, - 4, - 1h and - 5h versions cl= 3 0pf, f out=66.6mhz and measured at vdd/2 40.0 50.0 60.0 % dc-2 duty cycle, - 1, - 2, -3, - 4, - 1h and - 5h versions cl=15pf, fout<66.6mhz and measured at vdd/2 45.0 50.0 55.0 % dc-1 duty cycle. - 1, - 2, -3, - 4, - 1h and - 5h versions cl=30pf, fout=120mhz and measure d at vdd/2 tbd tbd tbd % dc-2 duty cycle. - 1, - 2, -3, - 4, - 1h and - 5h versions cl=15pf, fout=120mhz and measured at vdd/2 tbd tbd tbd % tr/f -1 rise and fall times. - 1, - 2, - 3, and - 4 versions measured between 0.8v and 2.0v cl=30pf - - 1.6 ns tr/f -2 rise a nd fall times. - 1, - 2, - 3, and - 4 versions measured between 0.8v and 2.0v cl=15pf - - 1.2 ns tr/f -3 rise and fall times. - 1,1h and - 5h versions measured between 0.8v and 2.0v cl=30pf - - 1.2 ns tr/f -3 rise and fall times. - 1h and - 5h versions measured b etween 0.8v and 2.0v cl=15pf - - 1.0 ns skw -1 output -to - output on same bank a or b . all versions all outputs are equally loaded . measured at vdd/2 - 60 150 ps skw -2 output bank - a to bank - b skew. -1 - 4 and - 5h versions all outputs are equally loaded . meas ured at vdd/2 - 60 150 ps skw -3 output bank - a to bank - b skew. -1 - 4 and - 5h versions all outputs are equally loaded . measured at vdd/2 - 130 300 ps skw -4 device - to - device skew. all versions all outputs are equally loaded . measured at vdd/2 and fbk pin - 180 500 ps tcfd clkin to fbk rising edge delay all outputs are equally loaded . measured at vdd/2 -200 - 200 ps t2 delay time, clkin rising edge to clkout rising edge (measured at vdd/2) [2] pll bypass mode 1.5 ? 4.4 ns pll enabled @ 3.3v ? 100 ? 100 ps pll enabled @2.5v ? 200 ? 200 ps t3 part -to - part skew [2] (measured at vdd/2) measured at vdd/2. any output to any output, 3.3v supply ? ? 150 ps measured at vdd/2. any output to any output, 2.5v supply ? ? 300 ps tlo ck pll lock time valid on all clock pins from vdd=2.97v - - 1.0 ms
rev 1.0, may 18, 2006 page 8 of 15 sl23ep08 ac electrical specifications : vdd=3.3 v+/ - 10% and - 40c to +85 c operation (industrial grade ) symbol description condition min typ max unit fout -1 output frequency cl=30pf, all devices 10 - 160 mhz fout -2 output frequency cl=20pf, - 1h and - 5h versions 10 - 220 mhz fout -2 output frequency cl=15pf, -1, -2, - 3 and - 4 versions 10 - 200 mhz dc-1 duty cycle. - 1, - 2, -3, - 4, - 1h and - 5h versions cl=30pf, f out=66.6mhz and measured at vd/2 40.0 50.0 60.0 % dc-2 duty cycle, - 1, - 2, -3, - 4, - 1h and - 5h versions cl=15pf, f out<66.6mhz and measured at vdd/2 45.0 50.0 55.0 % dc-1 duty cycle. - 1, - 2, -3, - 4, - 1h and - 5h versions cl=30pf, fout=120mhz and measured at vdd/2 tbd tbd tbd % dc-2 duty cycle. - 1, - 2, -3, - 4, - 1h and - 5h versions cl=15pf, fout=120mhz and measured at vdd/2 tbd tbd tbd % tr/f -1 rise and fall times. - 1, - 2, - 3, and - 4 versions measured between 0.8v and 2.0v cl=30pf - - 1.6 ns tr/f -2 rise and fall times. - 1, - 2, - 3, and - 4 versions measur ed between 0.8v and 2.0v cl=15pf - - 1.2 ns tr/f -3 rise and fall times. - 1,1h and - 5h versions measured between 0.8v and 2.0v cl=30pf - - 1.2 ns tr/f -3 rise and fall times. - 1h and - 5h versions measured between 0.8v and 2.0v cl=15pf - - 1.0 ns skw -1 out put -to - output on same bank a or b. all versions all outputs are equally loaded . measured at vdd/2 - 60 150 ps skw -2 output bank - a to bank - b skew. -1 - 4 and - 5h versions all outputs are equally loaded . measured at vdd/2 - 60 150 ps skw -3 output bank - a to bank - b skew. -1 - 4 and - 5h versions all outputs are equally loaded . measured at vdd/2 - 130 300 ps skw -4 device - to - device skew. all versions all outputs are equally loaded . measured at vdd/2 and fbk pin - 180 500 ps tcfd clkin to fbk rising edge delay all outputs are equally loaded . measured at vdd/2 -200 - 200 ps t2 delay time, clkin rising edge to clkout rising edge (measured at vdd/2) [2] pll bypass mode 1.5 ? 4.4 ns pll enabled @ 3.3v ? 100 ? 100 ps pll enabled @2.5v ? 200 ? 200 ps t3 part -to - part skew [2] (measured at vdd/2) measured at vdd/2. any output to any output, 3.3v supply ? ? 150 ps measured at vdd/2. any output to any output, 2.5v supply ? ? 300 ps tlock pll lock time valid on all clock pins from vdd= 2.97v - - 1.0 ms
rev 1.0, may 18, 2006 page 9 of 15 sl23ep08 ac electrical specifications: vdd=2.5 v+/ - 10% and 0c to +70c operation ( commercial grade ) symbol description condition min typ max unit fout -1 output frequency cl=30pf, all devices 10 - 160 mhz fout -2 output frequency cl=20pf, - 1h and - 5h versions 10 - 220 mhz fout -2 output frequency cl=15pf, -1, -2, - 3 and - 4 versions 10 - 200 mhz dc-1 duty cycle. - 1, - 2, -3, - 4, - 1h and - 5h versions cl=30pf, f out=66.6mhz and measured at vdd/2 40.0 50.0 60.0 % dc-2 duty cycle, - 1, - 2, -3, - 4, - 1h and - 5h versions cl=15pf, f out<66.6mhz and measured at vdd/2 45.0 50.0 55.0 % dc-1 duty cycle. - 1, - 2, -3, - 4, - 1h and - 5h versions cl=30pf, fout=120mhz and measured at vdd/2 tbd tbd tbd % dc-2 duty cycle. - 1, - 2, -3, - 4, - 1h and - 5h versions cl=15pf, fout=120mhz an d measured at vdd/2 tbd tbd tbd % tr/f -1 rise and fall times. - 1, - 2, - 3, and - 4 versions measured between 0.8v and 2.0v cl=30pf - - 1.6 ns tr/f -2 rise and fall times. - 1, - 2, - 3, and - 4 versions measured between 0.8v and 2.0v cl=15pf - - 1.2 ns tr/f -3 rise and fall times. - 1,1h and - 5h versions measured between 0.8v and 2.0v cl=30pf - - 1.2 ns tr/f -3 rise and fall times. - 1h and - 5h versions measured between 0.8v and 2.0v cl=15pf - - 1.0 ns skw -1 output -to - output on same bank a or b. all versions all outputs are equally loaded . measured at vdd/2 - 60 150 ps skw -2 output bank - a to bank - b skew. -1 - 4 and - 5h versions all outputs are equally loaded . measured at vdd/2 - 60 150 ps skw -3 output bank - a to bank - b skew. -1 - 4 and - 5h versions all outputs are equally loaded . measured at vdd/2 - 130 300 ps skw -4 device - to - device skew. all versions all outputs are equally loaded . measured at vdd/2 and fbk pin - 180 500 ps tcfd clkin to fbk rising edge delay all outputs are equally loaded . measured at vdd/2 -200 - 200 ps t2 delay time, clkin rising edge to clkout rising edge (measured at vdd/2) [2] pll bypass mode 1.5 ? 4.4 ns pll enabled @ 3.3v ? 100 ? 100 ps pll enabled @2.5v ? 200 ? 200 ps t3 part -to - part skew [2] (measured at vdd/2) measured at vdd/2. any output to any output, 3.3v supply ? ? 150 ps measured at vdd/2. any output to any output, 2.5v supply ? ? 300 ps tlock pll lock time valid on all clock pins from vdd=2.97v - - 1.0 ms
rev 1.0, may 18, 2006 page 10 of 15 sl23ep08 ac electrical specifications: vdd =2.5v+/ - 10% and - 40c to +85c operation (industrial grade ) symbol description condition min typ max unit fout -1 output frequency cl=30pf, all devices 10 - 160 mhz fout -2 output frequency cl=20pf, - 1h and - 5h versions 10 - 220 mhz fout -2 output frequenc y cl=15pf, -1, -2, - 3 and - 4 versions 10 - 200 mhz dc-1 duty cycle. - 1, - 2, -3, - 4, - 1h and - 5h versions cl=30pf, fout=66.6mhz and measured at vdd/2 40.0 50.0 60.0 % dc-2 duty cycle, - 1, - 2, -3, - 4, - 1h and - 5h versions cl=15pf, fout<66.6mhz and measured at vd d/2 45.0 50.0 55.0 % dc-1 duty cycle. - 1, - 2, -3, - 4, - 1h and - 5h versions cl=30pf, fout=120mhz and measured at vdd/2 tbd tbd tbd % dc-2 duty cycle. - 1, - 2, -3, - 4, - 1h and - 5h versions cl=15pf, fout=120mhz and measured at vdd/2 tbd tbd tbd % tr/f -1 rise an d fall times. - 1, - 2, - 3, and - 4 versions measured between 0.8v and 2.0v cl=30pf - - 1.6 ns tr/f -2 rise and fall times. - 1, - 2, - 3, and - 4 versions measured between 0.8v and 2.0v cl=15pf - - 1.2 ns tr/f -3 rise and fall times. - 1,1h and - 5h versions meas ured between 0.8v and 2.0v cl=30pf - - 1.2 ns tr/f -3 rise and fall times. - 1h and - 5h versions measured between 0.8v and 2.0v cl=15pf - - 1.0 ns skw -1 output -to - output on same bank a or b. all versions all outputs are equally loaded . measured at vdd/2 - 60 150 ps skw -2 output bank - a to bank - b skew. -1 - 4 and - 5h versions all outputs are equally loaded . measured at vdd/2 - 60 150 ps skw -3 output bank - a to bank - b skew. -1 - 4 and - 5h versions all outputs are equally loaded . measured at vdd/2 - 130 300 ps skw -4 device - to - device skew. all versions all outputs are equally loaded . measured at vdd/2 - 180 500 ps tcfd clkin to fbk rising edge delay all outputs are equally loaded . measured at vdd/2 -200 - 200 ps t2 delay time, clkin rising edge to clkout r ising edge (measured at vdd/2) [2] pll bypass mode 1.5 ? 4.4 ns pll enabled @ 3.3v ? 100 ? 100 ps pll enabled @2.5v ? 200 ? 200 ps t3 part -to - part skew (measured at vdd/2) measured at vdd/2. any output to any output, 3.3v supply ? ? 150 ps measured at vdd/2. any output to any output, 2.5v supply ? ? 300 ps tlock pll lock time valid on all clock pins from vdd=2.97v - - 1.0 ms
rev 1.0, may 18, 2006 page 11 of 15 sl23ep08 external components & design considerations typical application schematic sl23ep08 cl cl 0.1f 0.1f clkin fbk clka1 clkb4 gnd gnd s1 s2 vdd vdd 1 4 13 9 8 5 12 11 2 16 vdd clka2 3 cl-4pf comments and recommendations decoupling capacitor: a decoupling capacitor of 0 )pxvwehxvhgehwzhhq9''dqg966slqv3odfhwkhfdsdflwrurq the component side of the pcb as close to the vdd pin as possible. the pcb trace to the vdd pin and to the gnd via should be kept as short as possible. do not use vias between the decoupli ng capacitor and the vdd pin. series termination resistor : a series termination resistor is recommended if the distance between the output clocks and the load is over 1 ? inch. the nominal impedance of the clock outputs is given on the page 4. place the se ries termination resistors as close to the clock outputs as possible. zero delay and skew control: all outputs and clkin pins should be loaded with the same load to achieve ?zero delay? between the clkin and the outputs. the clkout pin is connected to clki n internally on - chip for feedback to pll, and sees an additional 4 pf load with respect to bank a and b clocks. for applications requiring zero input/output delay, the loa d at the all output pins including the clkout pin must be the same. if any delay adju stment is required, the capacitance at the clkout pin could be increased or decreased to increase or decrease the delay between bank a and b clocks and clkin. for minimum pin -to - pin skew, the external load at all the bank a and b clocks must be the same.
rev 1.0, may 18, 2006 page 12 of 15 sl23ep08 switching waveforms output vdd/2 vdd/2 output t 1 input vdd/2 vdd/2 clkout t 2 t 3 any output part 1 or 2 vdd/2 vdd/2 any output part 2 or 1 figure 2 . output to output skew figure 3 . input to output skew figure 4 . part - to - part skew
rev 1.0, may 18, 2006 page 13 of 15 sl23ep08 package drawing and dimensions 16- lead tssop ( 4.4mm) 0 . 190 ( 0 . 007 ) 0 . 300 ( 0 . 012 ) 0 . 090 ( 0 . 003 ) 0 . 200 ( 0 . 008 ) 8 9 6 . 250 ( 0 . 246 ) 6 . 500 ( 0 . 256 ) 4 . 300 ( 0 . 169 ) 4 . 500 ( 0 . 177 ) 2 . 900 ( 0 . 114 ) 3 . 100 ( 0 . 122 ) 0 . 850 ( 0 . 033 ) 0 . 950 ( 0 . 037 ) 0 . 050 ( 0 . 002 ) 0 . 150 ( 0 . 006 ) 1 . 100 ( 0 . 043 ) max 0 . 076 ( 0 . 003 ) 0 to 8 0 . 500 ( 0 . 020 ) 0 . 700 ( 0 . 027 ) 0 . 650 ( 0 . 025 ) bsc gauge plane dimensions are in milimeters ( inches ). top line : ( min ) and bottom line : ( max ) pin - 1 id seating plane 1 16 0 . 650 ( 0 . 025 ) bsc thermal characteristics parameter symbol condition min typ max unit thermal resistance junction to ambient ja still air - 80 - c/w ja 1m/s air flow - 70 - c/w ja 3m/s air flow - 68 - c/w thermal resistance junction to case jc independent of air flow - 36 - c/w
rev 1.0, may 18, 2006 page 14 of 15 sl23ep08 package drawing and dimensions (cont.) 8 0 . 150 ( 3 . 810 ) 0 . 157 ( 3 . 987 0 . 230 ( 5 . 842 ) 0 . 244 ( 6 . 197 ) 0 . 189 ( 4 . 800 ) 0 . 196 ( 4 . 978 ) 0 . 050 ( 1 . 270 ) bsc 0 . 004 ( 0 . 102 ) seating plane 0 . 004 ( 0 . 102 ) 0 . 0098 ( 0 . 249 ) 0 . 061 ( 1 . 549 ) 0 . 068 ( 1 . 727 ) 0 to 8 0 . 010 ( 0 . 2540 ) 0 . 016 ( 0 . 406 ) x 45 0 . 016 ( 0 . 406 ) 0 . 035 ( 0 . 889 ) 0 . 0075 ( 0 . 190 ) 0 . 0098 ( 0 . 249 ) pin - 1 id dimensions are in milimeters ( inches ). top line : ( min ) and bottom line : ( max ) 16 - lead soic ( 150 mil ) 1 9 16 0 . 0138 ( 0 . 350 ) 0 . 0192 ( 0 . 487 ) th ermal characteristics parameter symbol condition min typ max unit thermal resistance junction to ambient ja still air - 120 - c/w ja 1m/s air flow - 115 - c/w ja 3m/s air flow - 105 - c/w thermal resistance junction to case jc independent of air flow - 60 - c/w
rev 1.0, may 18, 2006 page 15 of 15 sl23ep08 ordering information [3 ] ordering number marking shipping package package temperature sl23ep08sc -1 sl23ep08sc -1 tube 16- pin soic 0 to 70c sl23ep08sc -1t sl23ep08sc -1 tape and reel 16- pin soic 0 to 70c sl23ep08si - 1 sl23ep08s i - 1 tube 16- pin soic - 40 to 85c sl23ep08si - 1t sl23ep08si - 1 tape and reel 16- pin soic - 40 to 85c sl23ep08sc -1h sl23ep08sc -1h tube 16- pin soic 0 to 70c sl23ep08sc - 1ht sl23ep08sc -1h tape and reel 16- pin soic 0 to 70c sl23ep08si - 1h sl23ep08si - 1h tube 1 6 - pin soic - 40 to 85c sl23ep08si - 1ht sl23ep08si - 1h tape and reel 16- pin soic - 40 to 85c sl23ep08zc - 1h sl23ep08zc - 1h tube 16 - pin tssop 0 to 70c sl23ep08zc - 1ht sl23ep08zc -1h tape and reel 16- pin tssop 0 to 70c sl23ep08zi - 1h sl23ep08zi - 1h tube 16 - pin tssop - 40 to 85c sl23ep08zi - 1ht sl23ep08zi -1h tape and reel 16- pin tssop - 40 to 85c sl23ep08sc - 2 sl23ep08sc - 2 tube 16 - pin soic 0 to 70c sl23ep08sc -2t sl23ep08sc -2 tape and reel 16- pin soic 0 to 70c sl23ep08si - 2 sl23ep08si - 2 tube 16- pin soic - 40 to 85c sl23ep08si - 2t sl23ep08si - 2 tape and reel 16- pin soic - 40 to 85c sl23ep08sc -3 sl23ep08sc -3 tube 16- pin soic 0 to 70c sl23ep08sc -3t sl23ep08sc -3 tape and reel 16- pin soic 0 to 70c sl23ep08si - 3 sl23ep08si - 3 tube 16- pin soic - 40 to 85c sl23ep08s i - 3t sl23ep08si - 3 tape and reel 16 - pin soic - 40 to 85c sl23ep08sc -4 sl23ep08sc -4 tube 16- pin soic 0 to 70c sl23ep08sc - 4t sl23ep08sc - 4 tape and reel 16 - pin soic 0 to 70c sl23ep08si - 4 sl23ep08si - 4 tube 16- pin soic - 40 to 85c sl23ep08si - 4t sl23ep08si - 4 tape and reel 16- pin soic - 40 to 85c sl23ep08sc -5h sl23ep08sc -5h tube 16- pin soic 0 to 70c sl23ep08sc - 5ht sl23ep08sc -5h tape and reel 16- pin soic 0 to 70c notes: 3. the sl23ep08 products are rohs compliant. the information in this document is b elieved to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences re sulting from the use of information included herein. additionally, silicon laboratories assumes no responsibility for the functioning of undescribed features or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims an y and all liability, including without limitation consequential or incidental damages. silicon laboratories products are not designed, intended, or authoriz ed for use in applications intended to support or sustain life, or for any other application in whic h the failure of the silicon laboratories product could create a situation where personal injury or death may occur. should buyer purchase or use silicon laboratories products for a ny such unintended or unauthorized application, buyer shall indemnify and h old silicon laboratories harmless against all claims and damages.

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